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ICs for Consumer Electronics
ADC with Built in Antialiasing filter and Clock generation UnitS ABACUS SDA 9206
Data Sheet 1999-02-10
Edition 1999-02-10 This edition was realized using the software system FrameMaker(R) Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1999. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
ICs for Consumer Electronics
ADC with Built in Antialiasing filter and Clock generation UnitS ABACUS SDA 9206
Data Sheet 1999-02-10
SDA 9206 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 21 21
Current Version: 1999-02-10
Subjects (major changes since last revision)
Update of Table 2 concerning Straight Binary
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA=25C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1999-02-10 Published by Siemens AG, Semiconductor Group Copyright (c) Siemens AG 1999. All rights reserved. Terms of delivery and right to change design reserved.
SDA 9206
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.2.1 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 3 3.1 3.2 4 5 5.1 5.2 5.3 6
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D Converter for YUV Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Signal Amplification, Prefiltering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Decimation Filters for YUV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Output Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Coding for Straight Binary / Two's Complement Mode . . . . . . . . . . Clock Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Horizontal PLL (HPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Vertical Sync Processing (only available for 1fh mode) . . . . . . . . . . . . . . . . Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Circuit Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 15 15 16 16 18 20 21 21 23 25 26 27 27 27 28 29 42
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 47 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram Data Input/Output Referenced to the Clock CLK1 . . . . . . . Timing Diagram Clock Skew CLK2 - CLK1 . . . . . . . . . . . . . . . . . . . . . . . . . Programmable Data Output Delay: DAT_OUT: Pins PAQ7...0, PBQ7...0, BLN, HS, H1I1, H2I2 and VS . . . . . . 52 52 52 53
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Semiconductor Group
5
1999-02-10
ADC with Built in Antialiasing filter and Clock generation UnitS ABACUS
Preliminary Data 1 1.1 * * * * * * * * * * Overview Features
SDA 9206
CMOS
* * * * * * * *
Three equivalent CMOS A/D converters on chip 30 MHz sampling rate 8-Bit resolution No external sample & hold required P-MQFP-64-3 Internal clamping circuits for each of the ADCs Internal amplification of input signals can be set by I2C Bus Internal pre-filtering of analog input signals High performance decimation filters Two data sampling modes (4:2:2 and 4:1:1) 3 output data interfaces - CCIR 656 interface (8 wires) - Parallel data interface (2 x 8 wires) - Quasi Parallel data interface (8 + 4 wires) Overflow and underflow I2C status bits On-chip sync and clock generation Separate SYNC input with clamping for sync and clock generation (max. line frequency of SYNC input: 38 kHz) positive and negative polarity of SYNC signal (switchable by I2C Bus) Lock-in behavior can be set via I2C Bus Frequency generator function possible with digitally adjustable frequency Clock generation for single and double line input frequencies supported (1fh / 2fh mode) Vertical noise suppression and 50/60 Hz detection (for 1fh mode only)
Type SDA 9206
Semiconductor Group
Ordering Code Q67101-H5185-A704
6
Package P-MQFP-64-3
1999-02-10
SDA 9206
* * * *
I2C-Bus interface
P-MQFP-64-3 5 V supply voltage for input signals 3.3 V or 5 V supply voltage for output signals General Description
1.2
The SDA 9206 is a single monolithic IC containing three separate 8-Bit A/D converters for video (YUV) applications and a clock sync generator which is delivering the sample clock for the A/D converters. It utilizes an advanced VLSI 0.5 m CMOS process providing 30 MHz sampling rates at 8-Bits. The YUV processing consists of following functional blocks: * * * * * Analog input buffers and clamping circuits Three 30 MHz A/D converters Digital decimation filters Delay compensation in Y-path Output formatter and buffer
The clock sync generator consists essentially of the following functional blocks: * Analog clamping * 7-Bit A/D converter * Sync processor with digital horizontal PLL, vertical sync processor and pulse generator * Clock generator with discrete timing oscillator, D/A converter, analog PLL and divider, as well as a crystal oscillator
Semiconductor Group
7
1999-02-10
SDA 9206
1.3
Pin Configuration
VSSDTO V DDQ VS CLK2 CLK1 HS VSSQ TEST EXSYN VAGNDPA VADDPA VAGNDC V REFLC SYNC V REFHC VADDC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 31 50 30 51 29 52 28 53 27 54 26 55 25 56 SDA 9206 24 57 23 58 22 59 21 60 20 61 19 62 18 63 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
X1 X2 V DDDTO V DD PBQ0 PBQ1 PBQ2 PBQ3 PBQ4 PBQ5 PBQ6 PBQ7 V SS ADR0 SDL SDA
V DDQ PAQ0 PAQ1 PAQ2 PAQ3 PAQ4 PAQ5 PAQ6 PAQ7 V SSQ V SS V DD H2I2 BLN RESOUTN H1I1
VADDY V REFHY AINY V REFLY VAGNDY VADDU V REFHU AINU V REFLU VAGNDU V ADDV V REFHV AINV V REFLV VAGNDV RESIN
UEP10457
Figure 1
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SDA 9206
1.4
Pin Description Symbol Type S S S S S I/ana Description Supply ground (VSS) for digital parts Supply voltage (VDD) for digital parts Supply ground for output stages and input stages Supply voltage for output stages and input stages (3.3 V / 5 V) Analog positive supply voltage of ADC AINY (5 V) Reference voltage high of ADC AINY (4.2 V) Analog voltage input of ADC AINY input range selectable via I2C Bus (subaddress 11H, YAMP) Reference voltage low of ADC AINY (2.2 V) S S I/ana Analog ground of ADC AINY Analog positive supply voltage of ADC AINU (5 V) Reference voltage high of ADC AINU (4.2 V) Analog voltage input of ADC AINU input range selectable via I2C Bus (subaddress 12H, UAMP) Reference voltage low of ADC AINU (2.2 V) S S I/ana Analog ground of ADC AINU Analog positive supply voltage of ADC AINV (5 V) Reference voltage high of ADC AINV (4.2 V) Analog voltage input of ADC AINV input range selectable via I2C Bus (subaddress 12H, VAMP) Reference voltage low of ADC AINV (2.2 V) S I/TTL/pu Q/TTL Analog ground of ADC AINV Reset input signal: active low Pin function defined by I2C Bus: Line frequent pulse output or programmable digital control output Reset output signal: active low; reset for other ICs Blanking signal output, high level indicates active video line
Pin No. 22, 36 21, 45 23, 55 32, 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VSS VDD VSSQ VDDQ VADDY VREFHY
AINY
VREFLY VAGNDY VADDU VREFHU
AINU
VREFLU VAGNDU VADDV VREFHV
AINV
VREFLV VAGNDV
RESIN H1I1
18 19
RESOUTN Q/TTL BLN Q/TTL
Semiconductor Group
9
1999-02-10
SDA 9206
1.4
Pin Description (cont'd) Symbol H2I2 Type Q/TTL Description Pin function defined by I2C Bus: Line frequent pulse output or programmable digital control output Data output Port A (see Data Format)
Pin No. 20
24 ... 31 33 34 35 37 ... 44 46 47 48 49 51 52 53 54 56
PAQ7 ... 0 Q/TTL SDA SCL ADR0 IQ I I/TTL/pd S Q/ana I/ana S Q/TTL Q/TTL Q/TTL Q/TTL I/TTL/pd
I2C-Bus data line I2C-Bus clock line I2C-Chip select
Data output port B (see Data Format) Positive supply voltage of DTO (5 V) Crystal connection Crystal connection (clock input) Ground of DTO Vertical sync pulse output Clock out: tristate / 6.75 / 13.5 / 27 MHz; selectable via I2C Clock out: tristate / 6.75 / 13.5 / 27 MHz; selectable via I2C Horizontal sync pulse output Input signal for test mode selection (0 V: no test mode selected) Leave unconnected or connect to VSS Input signal for test mode selection (0 V: no test mode selected) Leave unconnected or connect to VSS Analog ground of analog PLL and DACs Analog positive supply voltage of analog PLL and DACs (5 V) Analog ground of ADC SYNC Reference voltage low of ADC SYNC (2.2 V)
PBQ7... 0 Q/TTL
VDDDTO
X2 X1
VSSDTO
VS CLK2 CLK1 HS TEST
57
EXSYN
I/TTL/pd
58 59 60 61 62
VAGNDPA VADDPA VAGNDC VREFLC
SYNC I/ana
SYNC input Input range selectable via I2C Bus (subaddress 11H, SYNAMP)
Semiconductor Group
10
1999-02-10
SDA 9206
1.4
Pin Description (cont'd) Symbol Type Description Reference voltage high of ADC SYNC (4.2 V) Analog positive supply voltage of ADC SYNC (5 V) Q: output, TTL: digital (TTL) pd: internal pulldown-circuit
Pin No. 63 64 S: supply,
VREFHC VADDC
I: input,
ana: analog, 1.5
pu: internal pullup-circuit,
Internal Pin Configuration
Pin 2, 4, 7, 9, 12, 14, 61, 63 V REFHY , V REFLY , V REFHU , V REFLU , V REFHV , V REFLV ,
V REFLC , V REFHC
PAD
UES10549
Figure 2
Pin 17, 18, 19, 20, 24...31, 37...44, 51, 52, 53, 54 H1I1, RESOUTN, BLN, H2I2, PAQ7...0, PBQ7...0, VS, CLK2, CLK1, HS PAD
UES10550
Figure 3
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SDA 9206
Pin 16, 35, 56, 57 RESIN, ADR0, TEST, EXSYN
350 PAD
UES10551
Figure 4
Pin 33 SDA
350 PAD
UES10552
Figure 5
Pin 34 SCL
350 PAD
UES10553
Figure 6
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SDA 9206
Pin 3, 8, 13, 62 AINY, AINU, AINV, SYNC 350
PAD 350
UES10554
Figure 7
Pin 47, 48 X2, X1
350 PAD X2
350 PAD X1
UES10555
Figure 8
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SDA 9206
1.6
Block Diagram
V AGND V ADD
V SS
V DD
V SSQ
V DDQ
V REFHY AINY V REFLY V REFHU AINU V REFLU V REFHV AINV V REFLV
Clamping Circuit Triple 8 Bit 30 MHz ADC
Decimator 2:1
Delay
Delay
8
Port A
Decimator Stage 1 2:1
Decimator Stage 2 2:1
Decimator Stage 3 2:1
Output Formatter 8 Port B VS HS BLN CLK2 CLK1 H1I1 H2I2 RESOUTN
V REFHC SYNC V REFLC
RESIN
Sync Processing
Numerical Clock PLL
2 C Bus
V DDDTO V SSDTO
X1
X2 V AGNDPA V ADDPA ADR0
SCL SDA
UEB10456
Figure 9
Semiconductor Group
14
1999-02-10
SDA 9206
2 2.1
System Description A/D Converter for YUV Inputs
2.1.1 Introduction The SDA 9206 implements 3 independent 8-Bit A/D converters. Maximum conversion rate is 30 MHz. 2.1.2 Input Signal Amplification, Prefiltering The amplification of the input signals can be adjusted via I2C Bus. An internal prefiltering of the analog input signals is implemented. The typ. frequency response of the analog antialiasing prefilter is shown in figure 10.
0 dB -10 -20 -30 -40 -50 -60 -70 10 0 10 1
UED10458
5
5
MHz 10 2
Frequency
Figure 10 Frequency Response of the Analog Antialiasing Prefilter
Semiconductor Group
15
1999-02-10
SDA 9206
2.1.3 Clamping The analog pins AINY, AINU, AINV are switched simultaneously to on chip generated clamping levels by an on chip clamping pulse H2. Analog Channel AINY AINU, AINV Straight Binary Code 0001 0000 1000 0000 Two's Complement Code 1001 0000 0000 0000 Components Y U, V
The external clamping capacitance is loaded by on chip current sources during clamping. So loading time depends on the values of Cext cl . 2.1.4 Digital Decimation Filters for YUV The data rates of digital YUV signals are reduced in decimation filters following the A/D conversion. The overall performance of the decimation filters is tuned to the requirements for TV signals. In figure 11 the frequency response of the filter for the Y channel is shown. The input sampling rate is 27 MHz, the output sampling rate is 13.5 MHz.
10 dB 0 -10 -20 -30 -40 -50
UED10459
Amplitude
0
0.1
0.2
0.3
0.4
0.5
f / fS
Figure 11 Magnitude Frequency Response of the Luminance Filter The Input Sampling Frequency fS is 27 MHz
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SDA 9206
The total frequency response of the decimator stages 1 and 2 of the UV channels for an input sampling rate of 27 MHz and an output sampling rate of 6.75 MHz is shown in figure 12.
10
Amplitude
UED10460
dB 0 -10 -20 -30 -40 -50
0
0.1
0.2
0.3
0.4
0.5
f / fS
Figure 12 Magnitude Frequency Response for Chroma Signals (Decimator Stages 1 and 2) The Input Sampling Frequency fS is 27 MHz
Semiconductor Group
17
1999-02-10
SDA 9206
The frequency response of the decimator filter stage 3 of the UV channels for an input sampling rate of 6.75 MHz and an output sampling rate of 3.375 MHz is shown in figure 13. The decimator stage 3 is active for 4:1:1 mode and can also be activated for 4:2:2 mode by I2C Bus (control bit UV3FIL).
10
UED10461
Amplitude
dB 0 -10 -20 -30 -40 -50
0
0.1
0.2
0.3
0.4
0.5
f / fS
Figure 13 Frequency Response of the Chroma Decimator Stage 3 The Input Sampling Frequency fS is 6.75 MHz
2.2
Data Output Formatter
Three output data formats can be selected via I2C Bus (control Bits FORMAT). One format corresponds to CCIR 656 (8-Bit bus at a data rate of 27 MHz), an other format makes available Y and UV data separately on 2 parallel 8-Bit buses for Y and UV at a data rate of 13.5 MHz each. The third format is a 12-Bit bus with 8 connections for Y and 4 connections for multiplexed UV data.
Semiconductor Group
18
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SDA 9206
Output Quasiparallel Data Pin FORMAT = 10 or 11 (13.5 MHz) PAQ7 Y07 PAQ6 Y06 PAQ5 Y05 PAQ4 Y04 PAQ3 Y03 PAQ2 Y02 PAQ1 Y01 PAQ0 Y00 PBQ7 U07 PBQ6 U06 PBQ5 V07 PBQ4 V06 PBQ3 Z PBQ2 Z PBQ1 Z PBQ0 Z Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 Z Z Z Z Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 Z Z Z Z Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 Z Z Z Z
Parallel Data CCIR 656 FORMAT = 01 FORMAT = 00 (13.5 MHz) (27 MHz) Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 U07 U06 U05 U04 U03 U02 U01 U00 Z Z Z Z Z Z Z Z Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 Z Z Z Z Z Z Z Z V07 V06 V05 V04 V03 V02 V01 V00 Z Z Z Z Z Z Z Z Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Z Z Z Z Z Z Z Z
XAB: X: signal component Z: Pin is in tristate mode.
A: sample number
B: bit number
The BLN signal marks the active part of the video line (see figure 14).
CLK1
BLN
PAQ
U0
Y0
V0
Y1
PAQ, PBQ
Y0 / U0
Y1 / V0
UED10462
Figure 14
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SDA 9206
2.2.1 Output Coding for Straight Binary / Two's Complement Mode Straight binary or Two's complement output coding is selectable for each separate signal component (Y and UV) via I2C-Bus control bits YCODE and UVCODE. For straight binary coding a special suppression of code 0 and code 255 is provided in output format mode according CCIR 656. Table 1 Output Coding Step AINY AINU, AINV OFL UFL Straight Two's Bit Bit Binary Complement 7654 3210 7654 3210 0 1 0 0 0 * * 0 0 0 0 0000 0000 1000 0000 0000 0000 1000 0000 0000 0001 1000 0001 0000 0010 1000 0010 * * * *
Underflow < VCY - 0.125 V 0 1 2 * * 253
< VCU, V - 1.0 V
VCY - 0.125 V VCY - 0.117 V VCY - 0.109 V
* *
VCU, V - 1.0 V 0 VCU, V - 0.992 V 0 VCU, V - 0.984 V 0
* * * * 0 0 0 1
VCY + 1.859 V VCY + 1.867 V 254 VCY + 1.875 V 255 Overflow > VCY + 1.875 V >
VCU, V + 0.984 V VCU, V + 0.992 V VCU, V + 1.0 V VCU, V + 1.0 V
1111 1101 0111 1101 1111 1110 0111 1110 1111 1111 0111 1111 1111 1111 0111 1111
VCY, VCU, V: ext. clamping level during clamping at Cext cl on channel AINY
resp. AINU, AINV Table 1 is valid for VREFL = 2.2 V and VREFH = 4.2 V, xAMP = 0000
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SDA 9206
Table 2 Output Coding in Case of CCIR 656 Format, FORMAT = 00 Step AINY AINU, AINV OFL UFL Straight Two's Bit Bit Binary Complement 7654 3210 7654 3210 0 1 0 0 0 * * 0 0 0 0 0000 0001 1000 0000 0000 0001 1000 0000 0000 0001 1000 0001 0000 0010 1000 0010 * * * *
Underflow < VCY - 0.125 V 0 1 2 * * 253
< VCU, V - 1.0 V
VCY - 0.125 V VCY - 0.117 V VCY - 0.109 V
* *
VCU, V - 1.0 V 0 VCU, V - 0.992 V 0 VCU, V - 0.984 V 0
* * * * 0 0 0 1
VCY + 1.859 V VCY + 1.867 V 254 VCY + 1.875 V 255 Overflow > VCY + 1.875 V >
VCU, V + 0.984 V VCU, V + 0.992 V VCU, V + 1.0 V VCU, V + 1.0 V
1111 1101 0111 1101 1111 1110 0111 1110 1111 1110 0111 1111 1111 1110 0111 1111
VCY, VCU,V: ext. clamping level during clamping at Cext cl on channel AINY
resp. AINU, AINV Table 2 is valid for VREFL = 2.2 V and VREFH = 4.2 V, xAMP = 0000 2.3 Clock Sync Generation
The clock sync generator is a phase locked loop that locks on a horizontal SYNC input signal and generates the clock signals as well as additional control output signals. 2.3.1 Horizontal PLL (HPLL) The input signal SYNC may be either a CVBS signal or a composite sync signal. The polarity of the SYNC signal can be both positive or negative (I2C-Bit SYPOL). The edges of the SYNC input pulses should not be steeper than 100 ns. The frequency of the SYNC signal can be of normal or double line frequency (I2C-Bit 2FH). The SYNC is clamped before A/D conversion. For DC-input signals clamping can be disabled (I2C-Bit CLOF). A/D conversion takes place with 7 bits and a nominal frequency of 27 MHz. The digital HPLL filters the signal with a cutoff frequency of 1 MHz (2 MHz for 2fh mode). If 1fh mode is used the sampling frequency is decimated to 13.5 MHz. Following the low pass filtering a black- and sync bottom- level measurement takes place in order to calculate a threshold value. By means of this value the phase difference between the HPLL output and the SYNC input pulse is determined. Using a digital PI filter an increment is calculated from this for the Discrete Timing Oscillator (DTO). It is possible
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SDA 9206
to adapt the nominal frequency of the DTO by means of 5 I2C-Bus bits (INC4...INC0) such shifting the center frequency according to the momentary standard used. For the different applications the following values of INC are allowed (values valid for a crystal frequency of 24.576 MHz): Application PAL NTSC FH [Hz] 15625 15750 2FH 0 0 1 1 1 1 1 1 YUV-ADCs active active inactive inactive inactive inactive inactive inactive INC 6 6 6 6 8 11 14 21
PAL (100 Hz/VGA) 31250 NTSC (120 Hz/VGA) 31500 ATV MUSE Macintosh VGA 32400 33750 35000 38000
Note: A change of INC causes spontaneous changes of the generated clock frequencies!
The DTO generates a saw-tooth with a frequency that is proportional to the increment. The saw-tooth is converted into a sinusoidal clock signal by means of a D/A converter and applied to an analog PLL which multiplies the frequency and minimizes residual jitter. By means of the I2C bits S1CL and S2CL the output frequency on pins CLK1 and CLK2 can be set. In this manner a clock is provided that is line-locked with the SYNC-input signal. The ratio of these clock frequencies to the horizontal frequency of SYNC depends only on the I2C-Bus bits S1CL, S2CL, HPLL and 2FH. For the different modes the following values of S1CL and S2CL are allowed: Mode CCIR CCIR YUV-ADC 2FH enabled enabled 0 0 0 0 1 1 S1CL 11 11 11 10 01 10 S2CL 11 00 11 00 11 11
fCLK1
(MHz) 27 27 27 13.5
fCLK2
(MHz) 27 tristate 27 tristate
4:2:2, 4:1:1 enabled 4:2:2, 4:1:1 enabled VGA VGA disabled disabled
6.25 ... 8.75 25 ... 35 12.5 ... 17.5 25 ... 35
The digital horizontal PLL supplies a noise-suppressed horizontal pulse.
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During 1fh mode (2FH = 0) the digital HPLL also supplies a noise-suppressed vertical pulse obtained by digital integration of the main equalizing pulses. An integration time of 26.6 s or 11.3 s can be set by the I2C Bus. This functionality is switched off during 2fh mode (2FH = 1). 2.3.2 Vertical Sync Processing (only available for 1fh mode) Vertical sync processing consists of: * 625/525 line detection * vertical noise suppression The vertical pulses are obtained from the SYNC signal by integration. The 625/525 line detector measures the number of lines per field. By taking the average of the individual measurements with two up/down counters, the status bits 'FF' ad 'FFGF' are obtained. When vertical noise suppression is switched on (VOFF = 0), the vertical pulse obtained from the SYNC signal by integration is admitted only within a preset window (refer to timing diagram) and appears as a VS pulse. The width of the window can be set via the I2C Bus. In the temporary absence of vertical pulses in SYNC, a continuous VS can be generated by switching on a 'flywheel mode' (SCHW = 1) providing a number of lines per field of 312.5 or 262.5 respectively. When interference to SYNC is heavy, missing vertical pulses can be supplemented by switching on the flywheel mode and vertical interference can be eliminated by switching on the noise suppression circuitry. Noise suppression and the flywheel mode can be enabled independently of each other. There is also the possibility of generating VS in the free-running mode. The VS pulses are then completely independent of the vertical sync pulse in SYNC. When FREE = 1 and SCHW = 1, a VS pulse is generated every 262.5 or 312.5 lines (VF = 1 or 0 respectively). When FREE = 1 and SCHW = 0, a VS pulse is generated every 279 or 339 lines (VF = 1 or 0 respectively). Free-running generation of VS occurs every 262 or 312 in the terminal mode (TERM = 1).
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Non-Suppressed Vertical Sync from HPLL Line Number xxx
Interference Pulse
249
289
298 299 300 (249) (250)
311 312 (261) (262)
(199) (200) (239) (240) Window (VWIWI = 11) Window (VWIWI = 10) Window (VWIWI = 01) Window (VWIWI = 00) VS (noise-suppressed) Suppression of Interference Pulse not in Window
Vertical Sync Closes Window
Numbers in Brackets for 525 Lines per Frame
UED10463
When missing Vertical Sync from HPLL: Line Number 312 313 (262) VS SCHW = 0 Windows RC-Opening (Independent from WWW Bit) Numbers in Brackets for 525 Lines per Frame
UED10464
339
1
272 (242)
(279) (1)
Figure 15 Window for Vertical Pulse Noise Suppression
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2.3.3 Pulse Generation The clock sync generator supplies the following pulses: HS VS BLN Two clamping pulses H1 and H2. H2 is also the internal clamping pulse of the YUV-ADCs. * The HS pulse is 16 13.5 MHz clock periods long and can be shifted by the I2C-Bus in increments of four 13.5 MHz clock periods. * For the VS pulse refer to vertical noise suppression. * With the BLN pulse the start time (high-to-low edge) and the stop time (low-to-high edge) can be set within a certain range of lines in increments of 13.5 MHz clock periods by I2C Bus. The timing of BLN does not change during the field blanking interval. * During the BLN pulse the Y-U-V output data are set to their clamping level. * For pulse H1 the start time (low-to-high edge) and stop time can be set in increments of two 13.5 MHz clock periods. * For pulse H2 the start time (low-to-high edge) and stop time can be set in increments of 13.5 MHz clock periods. The timing of the BLN, H1, H2, VS and HS pulses can be set by the costumer using the specified I2C-Bus bits. Figure 9 shows the ranges of those settings.
Reference Time SYNC approx. 2.6 s HS HSON (-35.22 s ... 28.42 s) approx. 1.2 s H1 H2 H1ON (-28.27 s ... 9.47 s) H2ON (-4.67 s ... 14.21 s) BON (-8.89 s ... 9.99 s) BLN All times are given in relation to the Reference Time! All times are only valid for 2FH = 0. If 2FH = 1 all times have to be divided by two! H1OF (-28.27 s ... 9.47 s) H2OF (-4.67 s ... 14.21 s) BOF (0.59 s ... 19.46 s)
UET10465
* * * *
BURST
Figure 16 I2C-Bus Programming Areas of Horizontal-Frequency Pulses
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2.3.4 Miscellaneous Circuit Sections To suppress bottom flutter in VCR mode, the frequency of the clock can be 'hold' by 'freezing' the increment of the HPLL. The vertical-frequency 'freezing-time' starts a number of lines (programmable by the I2C Bus) before the vertical pulse and then lasts for a number (programmable) of lines. The settings do not depend on I2C-Bit TV. This functionality is only available for the 1fh mode (2FH = 0).
VS
Line Number of Half Picture
n-2
n-1
n
1
2
3
4
5
Start 0...15 Lines before VS 15 14 13 Start Range over which Frequency Value is Frozen 0 1 10 Stop 12 3 2 1 0
n = Number of Lines in preceding Half Picture
0...15 Lines Duration 12 13 14 15
11
(In this example the frequency value was frozen 13 lines before the VS pulse and for a duration of 11 lines.) UED10466
Figure 17 I2C-Bus Programming Area which Clock Frequency Value Generated by HPLL can be Frozen An active low reset signal for other chips is available at pin RESOUTN. It is activated when the chip supply voltage VDD is switched on or when voltage glitches occur on it. RESOUTN also is activated by pin RESIN. The RESOUTN pulse signal is not cancelled until the crystal oscillator resonates and in addition stretched by an internal circuit for approximately 127 lines (8 ms).
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2.4
I2C Bus
2.4.1 I2C-Bus Address 101100B 2.4.2 I2C-Bus Format Write: S101100B0A Read: S101100B1A *** Status Byte 0 A Status Byte 1 ***** A Data **** Subaddress A Data Byte A ***** A P B: equal to the value set on pin ADR0
**** Byte n A Data Byte (n+1) A
NA P
Reading starts with status byte 0, followed by status byte 1 and then in succession by data byte n, data byte n+1..., where n is the last write address. Specification of a subaddress in reading mode is not possible. S: A: P: NA: Start condition Acknowledge Stop condition Not Acknowledge
An automatic address increment function is implemented. After switching on the IC or RESIN = 0, all bits are set to defined states. Particularly: Register 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH
Semiconductor Group
Default value 10H 40H 00H 00H 28H 00H 00H 06H 00H 00H 00H 00H
Register 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H
27
Default value 00H 00H 00H 00H 00H 00H 00H 00H 13H 00H 00H 00H
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2.4.3 I2C-Bus Commands
Data Byte Subadd. D7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 0 YD3 I2 0 0 0 TV 2FH BON7 BOF7 H1ON7 H1OF7 H2ON7 H2OF7 HSON7 0 FION3 D6 UV3FIL YD2 I1 0 OEFB SCHW FREE HSWMA BON6 BOF6 H1ON6 H1OF6 H2ON6 H2OF6 HSON6 0 FION2 D5 D4 D3 D2 YCODE 0 0 CGSUP0 S2CL0 0 GENMOD INC2 BON2 BOF2 H1ON2 H1OF2 H2ON2 H2OF2 HSON2 0 FILE2 YAMP2 VAMP2 D1 OENB 0 0 VWIWI1 0 0 0 INC1 BON1 BOF1 H1ON1 H1OF1 H2ON1 H2OF1 HSON1 0 FILE1 YAMP1 VAMP1 D0 OENA 0 0 VWIWI0 0 0 SYPOL INC0 BON0 BOF0 H1ON0 H1OF0 H2ON0 H2OF0 HSON0 0 FILE0 YAMP0 VAMP0 0 1 0 0 0
FORMAT1 FORMAT0 UVCODE YD1 SELH2I2 0 S1CL1 HPLL VOFF HSWMIN BON5 BOF5 H1ON5 H1OF5 H2ON5 H2OF5 HSON5 0 FION1 YD0 SELH1I1 0 S1CL0 VTHRE VF INC4 BON4 BOF4 H1ON4 H1OF4 H2ON4 H2OF4 HSON4 0 FION0 0 0 CGSUP1 S2CL1 CLOF TERM INC3 BON3 BOF3 H1ON3 H1OF3 H2ON3 H2OF3 HSON3 0 FILE3
SYNAMP3 SYNAMP2 SYNAMP1 SYNAMP0 YAMP3 UAMP3 DATDEL2 0 0 0 0 UAMP2 DATDEL1 0 0 0 0 UAMP1 DATDEL0 0 0 0 0 UAMP0 DATSLOP 1 0 0 0 VAMP3
CLKSLOP1 CLKSLOP0 0 0 0 0 0 0 0 0 0 1 0 0 0
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2.4.4 Detailed Description Subaddress 00H Bit D7 D6 Name 0 UV3FIL Function Reserved Filter stage 3 for UV data (FORMAT = 0X) OFF 0: 1: ON
Note: For FORMAT = 1X filter stage 3 for UV data is "on" (UV3FIL = dont care)
D5...D4 FORMAT Selection of output data interface: 00: Output data format according CCIR 656 (8 wires at Port A) 01: Parallel output data format (2 x 8 wires) 10: Quasiparallel 12 wire interface 11: Quasiparallel 12 wire interface UVCODE Coding of UV data: Straight binary code 0: 1: Two's complement code YCODE Coding of Y data: Straight binary code 0: 1: Two's complement code Output enable port B: Tristate 0: 1: Port enabled Output enable port A: Tristate 0: 1: Port enabled
D3
D2
D1
OENB
D0
OENA
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Subaddress 01H Bit D7...D4 Name YD Function Delay compensation in Y-signal path (13.5 MHz clocks): 0000: ... - 0.30 s 0001 0010 0011 0100: ... 0 s : : 1110 1111: ... 0.81 s
D3...D0
0000
Reserved
Subaddress 02H Bit D7 Name I2 Function Voltage level of H2I2 output (SELH2I2 = 1): 0: Low voltage at pin H2I2 1: High voltage at pin H2I2 Voltage level of H1I1 output (SELH1I1 = 1): Low voltage at pin H1I1 0: 1: High voltage at pin H1I1 Function of pin H2I2: H2 (line frequency, start and stop programmable) 0: 1: I2 (low/high programmable) Function of pin H1I1: H1 (line frequency, start and stop programmable) 0: 1: I1 (low/high programmable) Reserved Reserved Reserved Reserved
D6
I1
D5
SELH2I2
D4
SELH1I1
D3 D2 D1 D0
0 0 0 0
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Subaddress 03H Bit D7...D4 D3...D2 Name 0000 CGSUP Function Reserved Suppression of black level disturbances caused by copy guarded tapes No function 00: 01: Black level error is limited to + / - 32 (~ 27 mV) 10: Black level error is limited to + / - 16 (~ 14 mV) 11: Black level error is limited to + / - 8 (~ 7 mV) Width of Window in Vertical Processing: 00: Narrow window: open from line 312 for PAL and 262 for NTSC 01: Window: open from line 300 for PAL and 250 for NTSC 10: Window: open from line 290 for PAL and 240 for NTSC 11: Very wide window: open from line 250 for PAL and 200 for NTSC
D1...D0
VWIWI
Subaddress 04H Bit D7 D6 Name 0 OEFB Function Reserved Output enable for Featurebox signals BLN, HS and VS: BLN, HS, VS outputs tristate 0: 1: BLN, HS, VS outputs enabled (2FH = 0) BLN, HS outputs enabled, VS output tristate (2FH = 1) D5...D4 S1CL Selection of clock frequency on pin CLK1: 00: Tristate 01: 6.75 MHz 13.5 MHz 10: 11: 27 MHz For the allowed values of S1CL refer to table chapter 2.3.1! D3...D2 S2CL Selection of clock frequency on pin CLK2: 00: Tristate 01: 6.75 MHz 13.5 MHz 10: 11: 27 MHz For the allowed values of S2CL refer to table chapter 2.3.1! D1...D0 00 Reserved
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Subaddress 05H Bit D7 D6 Name 0 SCHW Function Reserved Mode of vertical pulse generation: No flywheel mode 0: 1: Flywheel mode Relationship between horizontal frequency in SYNC and default frequency on CLK1 and CLK2: 0: 864 1: 858 Minimum sync pulse length from which a vertical pulse is detected: 0: 26.6 s 1: 11.3 s Clamping of SYNC for clock generator: Clamping on 0: 1: Clamping off Reserved
D5
HPLL
D4
VTHRE
D3
CLOF
D2...D0
000
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Subaddress 06H Bit D7 Name TV Function Selection of HPLL lock-in behavior: 0: Optimum for VCR 1: Optimum for SYNC from network Generation of V pulse: V derived from SYNC 0: 1: Free-running generation; vertical frequency is determined by VF bit, VOFF bit is enabled, SCHW bit should be set to 1 Vertical noise suppression: 0: Noise suppression enabled 1: No noise suppression Number of lines per field: 312.5 or 312 0: 1: 262.5 or 262
D6
FREE
D5
VOFF
D4
VF
Note: VF must be set to the number of lines present in SYNC for fly-wheel and noise suppression modes. VF determines the number of lines per field for the free-running or terminal mode.
D3 TERM Terminal mode: FREE TERM SCHW VF Number of Lines per Field generated in Free-Running Mode 312 262 312.5 262.5 339 279
don't care don't care 1 1 1 1 D2
1 1 0 0 0 0
don't care don't care 1 1 0 0
0 1 0 1 0 1
GENMOD Clock generator mode Normal PLL mode 0: 1: Generator mode (fixed frequency output, controlled by INC) 0 SYPOL Reserved SYNC polarity: Negative sync signals (normal SYNC input) 0: 1: Positive sync signals
D1 D0
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Subaddress 07H Bit D7 Name 2FH Function Selection of input frequency range: 0: Normal line frequencies (around 15.6 kHz) 1: Double line frequencies (31.2...38 kHz) [YUV A/D converters are switched off] Maximum width of HSYNC (input SYNC): 6.2 s for low FH-range 0: 3.1 s for high FH-range (2FH = 1) 1: 9.0 s for low FH-range 4.5 s for high FH-range (2FH = 1) Minimum width of HSYNC (input SYNC): 3.0 s for low FH-range 0: 1.5 s for high FH-range (2FH = 1) 1: 1.7 s for low FH-range 0.8 s for high FH-range (2FH = 1) Nominal PLL output frequency: INC = 00110 For the allowed values of INC refer to table chapter 2.3.1! Calculation of INC for low FH range:
D6
HSWMA
D5
HSWMI
D4...D0
INC
fh INC = INT --- * 110592 - 64 ,625 f
q
for high FH range (2FH = 1):
fh INC = INT --- * 55292 - 64 ,625 f
q
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Subaddress 08H Bit D7...D0 Name BON Function BLN start time in relation reference time (refer to the following table and to timing diagram) Number - (- 128) + 7 ... - (- 1) + 7 - (0) + 7 - (+ 1) + 7 ... - (+ 127) + 7 13.5 MHz Cycles = 135 ... =8 =7 =6 ... = - 120 Time (2FH = 0) 9.99 s ... 0.60 s 0.52 s 0.44 s ... - 8.89 s
BON7...BON0 1000 0000 ... 1111 1111 0000 0000 0000 0001 ... 0111 1111 Subaddress 09H Bit D7...D0 Name BOF
Function BLN stop time in relation to reference time: (refer to the following table and to timing diagram) Number (0) + 8 (+ 1) + 8 ... (+ 127) + 8 (+ 128) + 8 (+ 129) + 8 ... (+ 254) + 8 (+ 255) + 8 13.5 MHz Cycles =8 =9 ... = 135 = 136 = 137 ... = 262 = 263 Time (2FH = 0) 0.59 s 0.67 s ... 9.99 s 10.06 s 10.14 s ... 19.39 s 19.46 s
BOF7...BOF0 0000 0000 0000 0001 ... 0111 1111 1000 0000 1000 0001 ... 1111 1110 1111 1111
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Subaddress 0AH Bit D7...D0 Name H1ON Function H1 start time in relation to reference time: (refer to the following table and to timing diagram) Number - (- 64) x 2 ... - (- 1) x 2 - (0) x 2 - (+ 1) x 2 ... - (+ 127) x 2 - (+ 128) x 2 - (+ 129) x 2 ... - (+ 191) x 2 13.5 MHz Cycles = 128 ... =2 =0 =-2 ... = - 254 = - 256 = - 258 ... = - 382 Time (2FH = 0) 9.47 s ... 0.15 s 0 s - 0.15 s ... - 18.79 s - 18.94 s - 19.09 s ... - 28.27 s
H1ON7...H1ON0 1100 0000 ... 1111 1111 0000 0000 0000 0001 ... 0111 1111 1000 0000 1000 0001 ... 1011 1111 Subaddress 0BH Bit D7...D0 Name H1OF
Function H1 stop time in relation to reference time: (refer to the following table and to timing diagram) Number - (- 64) x 2 ... - (- 1) x 2 - (0) x 2 - (+ 1) x 2 ... - (+ 127) x 2 - (+ 128) x 2 - (+ 129) x 2 ... - (+ 191) x 2
36
H1OF7...H1OF0 1100 0000 ... 1111 1111 0000 0000 0000 0001 ... 0111 1111 1000 0000 1000 0001 ... 1011 1111
Semiconductor Group
13.5 MHz Cycles = 128 ... =2 =0 =-2 ... = - 254 = - 256 = - 258 ... = - 382
Time (2FH = 0) 9.47 s ... 0.15 s 0 s - 0.15 s ... - 18.79 s - 18.94 s - 19.09 s ... - 28.27 s
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Subaddress 0CH Bit D7...D0 Name H2ON Function H2 start time in relation to reference time: (H2 is always used as clamping reference for the YUV ADCs) (refer to the following table and to timing diagram) Number - (- 192) ... - (- 129) - (- 128) - (- 127) ... - (- 1) - (0) - (+ 1) ... - (+ 63) 13.5 MHz Cycles = 192 ... = 129 = 128 = 127 ... =1 =0 =-1 ... = - 63 Time (2FH = 0) 14.21 s ... 9.55 s 9.47 s 9.40 s ... 0.07 s 0 s - 0.07 s ... - 4.67 s
H2ON7...H2ON0 0100 0000 ... 0111 1111 1000 0000 1000 0001 ... 1111 1111 0000 0000 0000 0001 ... 0011 1111
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Subaddress 0DH Bit D7...D0 Name H2OF Function H2 stop time in relation to reference time: (H2 is always used as clamping reference for the YUV ADCs) (refer to the following table and to timing diagram) Number - (- 192) ... - (- 129) - (- 128) - (- 127) ... - (- 1) - (0) - (+ 1) ... - (+ 63) 13.5 MHz Cycles = 192 ... = 129 = 128 = 127 ... =1 =0 =-1 ... = - 63 Time (2FH = 0) 14.21 s ... 9.55 s 9.47 s 9.40 s ... 0.07 s 0 s - 0.07 s ... - 4.67 s
H2OF7...H2OF0 0100 0000 ... 0111 1111 1000 0000 1000 0001 ... 1111 1111 0000 0000 0000 0001 ... 0011 1111 Subaddress 0EH Bit D7...D0 Name HSON
Function HS start time in relation to reference time: (refer to the following table and to timing diagram) Number - (- 96) x 4 ... - (- 1) x 4 - (0) x 4 - (+ 1) x 4 ... - (+ 118) x 4 - (+ 119) x 4 13.5 MHz Cycles = 384 ... =4 =0 =-4 ... = - 472 = - 476 Time (2FH = 0) 28.42 s ... 0.30 s 0 s - 0.30 s ... - 34.93 s - 35.22 s
HSON7...HSON0 1010 0000 ... 1111 1111 0000 0000 0000 0001 ... 0111 0110 0111 0111
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Subaddress 0FH Bit D7...D0 Name Function 0000 0000 Reserved
Subaddress 10H Bit D7...D4 Name FION Function Start of clock frequency freezing in number of lines before the vertical pulse (only valid for 2FH = 0): 0000: 0 (no freezing) 0001: 1 : : 1111: 15 Duration of clock frequency freezing in number of lines: 0000: 0 (no freezing) 0001: 1 : : 1111: 15
D3...D0
FILE
Subaddress 11H Bit D7...D4 Name Function Allowed values: SYNAMP = 0000 : amplification 0 dB : SYNC input nom. 2 Vpp SYNAMP = 0110 : amplification 6 dB : SYNC input nom. 1 Vpp D3...D0 YAMP Internal amplification of AINY input signal. Allowed values: YAMP = 0000 : amplification 0 dB : AINY input nom. 2 Vpp YAMP = 0110 : amplification 6 dB : AINY input nom. 1 Vpp SYNAMP Internal amplification of SYNC input signal.
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Subaddress 12H Bit D7...D4 Name UAMP Function Internal amplification of AINU input signal. Allowed values: UAMP = 0000 : internal amplification 0 dB : AINU input nom. 2 Vpp UAMP = 0110 : internal amplification 6 dB : AINU input nom. 1 Vpp D3...D0 VAMP Internal amplification of AINV input signal. Allowed values: VAMP = 0000 : amplification 0 dB : AINV input nom. 2 Vpp VAMP = 0110 : internal amplification 6 dB : AINV input nom. 1 Vpp Subaddress 13H Bit D7...D5 Name DATDEL Function Programmable output delay for PAQ7...PAQ0, PBQ7...PBQ0, BLN, HS, H1I1, H2I2, VS. Allowed values: 000 001 (description see chapter 5.3) D4 DATSLOP Adaptation of the output driver stages for PAQ7...PAQ0, PBQ7...PBQ0, BLN, HS, H1I1, H2I2, VS. Allowed values: 0 ... to be used only for 5 V output stage supply voltage 1 ... to be used only for 3.3 V output stage supply voltage and FORMAT = 00 D3...D2 CLKSLOP Adaptation of the output driver stages for CLK1 and CLK2. Allowed values: 00 ... to be used only for 5 V output stage supply voltage 10 ... to be used only for 3.3 V output stage supply voltage D1...D0 00 Reserved
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Subaddress 14H Bit D7...D0 Name Function 0001 0011 Reserved
Subaddress 15H Bit D7...D0 Name Function 0000 0000 Reserved
Subaddress 16H Bit D7...D0 Name Function 0000 0000 Reserved
Subaddress 17H Bit D7...D0 Name Function 0000 0000 Reserved
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2.4.5 Read Mode Status Byte 0 Bit D7 Name CON Function Absolute difference between the horizontal sync pulse in SYNC and the HPLL: 0: Larger than or equal to 32 system clock cycles 1: Less than 32 system clock cycles
D6
THRELIM Absolute difference between the horizontal sync pulse in SYNC and the HPLL: 0: Larger than 8 system clock cycles 1: Less than 8 system clock cycles for 8 or more successive lines (i.e. HPLL well locked in) FFGF, FF Identified number of lines per field (refer also to timing diagram figure 16): < N1 N1 and N2 > N2 and < 287 287 and < N3 N3 and N4 > N4 VWIWI1 0 0 1 1 VWIWI0 0 1 0 1 N1 262 250 240 200 Status Bits FFGF FF
D5, D4
0 1 0 0 1 0 N2 264 275 285 312 N3 312 300 290 250
0 0 0 1 1 1 N4 314 325 335 362
N1 to N4 depends on Control Bits VWIWI:
D3 D2 ... D0 POR
dont care Status bit POR is set by power on reset or by activating the reset pin. POR is reset after reading the status byte.
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Status Byte 1 Bit D7...D6 D5 D4 D3 D2 D1 D0 OFLY UFLY OFLU UFLU OFLV UFLV Name Function dont care Overflow detection of ADC for input AINY Underflow detection of ADC for input AINY Overflow detection of ADC for input AINU Underflow detection of ADC for input AINU Overflow detection of ADC for input AINV Underflow detection of ADC for input AINV
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3
Absolute Maximum Ratings Symbol min. Limit Values max. 125 260 10 C C sec Not valid for I2C-Bus pins - 40 Unit Remark
Parameter Storage temperature Soldering time Input/output voltage
Tstg tsold VI/Q
Soldering temperature Tsold
VSSQ - 0.3 V VDDQ + 0.3 V 1 VSSQ - 0.3 V 6 V
1
Input/output voltage VI/Q, I2C I2C-pins 33, 34 (SCL, SDA) Power supply voltage VDD,
- 0.3
6
V
VADDx, VDDQ, VDDDTO
Total power dissipation Ptot Latch-up protection ESD protection ESD - 100 -1 1.25 100 1 W mA kV All inputs/outputs MIL STD 883C method 3015-6, 100 pF, 1500
All voltages listed are referenced to ground (0 V, VSS) except where noted.
Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied.
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3.1
Recommended Operating Conditions Symbol min. 0 4.75 4.75 4.75 4.75 3.0 Limit Values nom. 25 5.0 5.0 5.0 5.0 3.3 max. 70 5.25 5.25 5.25 5.25 3.6 C V V V V V 5 V-Mode 3.3 V mode, only to be used for FORMAT = 00 Supply pins VADDx Unit Remark
Parameter
Ambient temperature TA Power Requirements Analog supply voltage VADDx Digital supply voltage VDD DTO supply voltage Output stage supply voltage
VDDDTO VDDQ
Supply voltage differential All TTL Inputs H-input voltage L-input voltage H-input voltage L-input voltage SCL clock frequency Rise times of SCL, SDA Fall times of SCL, SDA Set-up time data Hold time data Bus free time before start condition Set-up time start condition Hold time start condition
VDD, diff - 0.25
0.25
V
VIH VIL VIH VIL fSCL tR tF tSU, Dat tHD, Dat tBuf tSU, Sta tHD, Sta
2.0V 0 0.7 x VDDQ 0V 0
VDDQ
0.8
1 V 1 kHz
I2C-Bus (Values are Referred to min. (VIH) and max. (VIL)) VDD
400 0.3 0.3 100 0 1.3 0.6 0.6 0.3 x VDDQ 1
s s
ns ns
s s
s
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3.1
Recommended Operating Conditions (cont'd) Symbol min. Limit Values nom. max. 1.3 0.6 400 3.2 1.7 4.2 2.2 2V 4.7 3.2 Unit Remark
Parameter SCL low time SCL high time Load capacitance
tLow tHigh
s s
pF V V 1 YAMP, UAMP, VAMP = 0000, Prefiltering see chapter 2.1.2 AINY, AINU, AINV each
Reference Inputs for Analog Inputs AINY, AINU, AINV, SYNC Reference voltage high VREFHx Reference voltage low VREFLx Input range (Peak-Peak)
VADDx = 5 V
Analog Inputs AINY, AINU, AINV
VIPP
VREFHx VREFLx
Required ext clamp capacitance Required signal source resistance Input range (Peak-Peak) Input frequency Required ext clamp capacitance Required signal source resistance Crystal frequency Equivalent parallel C Crystal resonant impedance Pin capacitance
Cext cl RS
0
100 200
nF
SYNC Input for Sync and Clock Generation
VIPP
f
0.5 V 0
2V
VREFHCVREFLC
12
1 MHz nF
SYNAMP = 0000 To avoid aliasing
Cext cl RS
100 200
Inputs Crystal Connections X1, X2
fc CO ZR CI
24.576 3.6 40 10 18
MHz pF
Crystal Type Fundamental Crystal
pF pF Each
External capacitance Cext
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3.2
Characteristics (Assuming Recommended Operating Conditions) Symbol min. Limit Values nom. 120 40 40 max. mA mA mA Sum of all VADDx pins Sum of all VDD pins + VDDDTO Sum of all VDDQ pins Unit Remark
Parameter Supply Currents
Analog supply current IADD Digital supply current IDD Output stage supply current Reference ladder resistance
IDDQ
Reference Inputs for Analog Inputs AINY, AINU, AINV
RREF
175
250
325
For each converter between REFH and REFL For each converter between REFH and REFL
Reference Inputs for Analog Input SYNC Reference ladder resistance All TTL Inputs Input current - 300 300
RREF
280
400
520
A
VI = 0 V...VDDQ Note: internal pullup/ pulldown-circuits I = 4 mA
AINY, AINU, AINV, SYNC each AINY, AINU, AINV, SYNC each
I2C Input/Output SDA
L-output voltage Analog Inputs Analog input leakage IAIN current Analog input capacitance L-output voltage H-output voltage - 100 100 10 nA pF
VQL
0.6
V
CI
TTL Outputs Port A, Port B, VS, HS, BLN, H1, H2, RESOUTN (VDDQ = 3.3 V or 5 V)
VQL VQH
0 2.4 V - 20
0.4
V 1
I = 1 mA I = - 0.5 mA VQ = 0 V...VDDQ
Port A, Port B, VS, HS, BLN
VDDQ
20
High impedance state IQZ output current Load capacitance
Semiconductor Group
A
CL
47
25
pF
1999-02-10
SDA 9206
3.2
Characteristics (Assuming Recommended Operating Conditions) (cont'd) Symbol min. Limit Values nom. max. 25 ns DATDEL = 000 CL = 15 pF 5 V output stage supply voltage, DATSLOP = 0 DATDEL = 000 CL = 25 pF 5 V output stage supply voltage, DATSLOP = 0 DATDEL = 000 CL = 25 pF 3.3 V output stage supply voltage, FORMAT = 00 DATSLOP = 1 Unit Remark
Parameter
Output data delay time, tQD referenced to CLK1 (not valid for ESOUTN)
35
ns
25
ns
Output data hold time, tQH referenced to CLK1 (not valid for RESOUTN) Pin RESOUTN Data delay/ data hold time L-output voltage H-output voltage Load capacitance Transition times
6
ns
-
-
-
Asynchronous output signal
Clock TTL Outputs CLK1, CLK2
VQL VQH CL t R, t F
0 2.4 V
0.4
V 1 pF ns
I = 1 mA I = - 0.5 mA
5 V output stage supply voltage, CLKSLOP = 00 3.3 V output stage supply voltage, CLKSLOP = 10
VDD
30 5
Semiconductor Group
48
1999-02-10
SDA 9206
3.2
Characteristics (Assuming Recommended Operating Conditions) (cont'd) Symbol min. Limit Values nom. max. ns ns ns ns 0 27 2 35 ns MHz 13.5 MHz 13.5 MHz 27 MHz 27 MHz 26 26 10 10 -2 25 Unit Remark
Parameter Low time 13.5 MHz High time 13.5 MHz Low time 27 MHz High time 27 MHz Skew
tWL13 tWH13 tWL27 tWH27 tSK
CL,CLK1 = CL,CLK2
4.8% at 27 MHz S1CL = 11, S2CL = 11
Frequency range f when PLL is locked at SYNC input signal
Performance of A/D Conversion (8-Bit) Test Conditions: ADC Clock = 27 MHz, DATDEL = 000, xAMP = 0000, VIPP = 2 Vpp Sampling rate Differential linearity (DC) Clamping level accuracy Gain error (DC) Gain matching error (DC) Differential gain Differential phase Signal to noise ratio at 4.4 MHz sinus Harmonic Distortion 2./4. order 3. order 5./6. order - 42 - 42 - 48 dB dB dB 4.4 MHz fundamental 4.4 MHz fundamental 4.4 MHz fundamental DNLE 27 0.5 1 0.5 3 6 3 3 3 45 48 MHz LSB LSB LSB LSB LSB % deg dB Not tested Not tested Without harmonics
Integral linearity (DC) INLE CLA GE GME DG DP
S/N
Semiconductor Group
49
1999-02-10
SDA 9206
4
Application Information
YI 3ADC CSG 8 27 MHz VI SDA 9206 SDA 9290 Picture Processor
SDA 9251-2X
4 YOUT
UI
12 SDA 9253 12 SDA 9253
Field Mixer 16
Display Processor UOUT
SDA 9270 4
SDA 9280
VOUT
CVBS / SYNC
SDA 9251-2X
SYNC
MSC SDA 9220
SYNCOUT
UES10470
Figure 18 Application Circuit 1
27 MHz YIN 12 UIN VIN CVBS SYNC SDA 9206 YUV HIN VIN SDA 9255 HREF SDA 9280 Scan Rate Converter 12 YUV Display Provessor
CLK
YOUT UOUT VOUT SYNCOUT
UES10471
Figure 19 Application Circuit 2
Semiconductor Group 50 1999-02-10
SDA 9206
L3
+5 V
L2
10 H
+
L1 2.2 H
R4 8.2 / 2%
C 35 100 nF C 54 100 nF C 55 100 nF C 56 100 nF C 12 100 nF
100 nF 100 nF 100 nF
C 11 10 F 1 5 6 10 11 15 64 60 59 58
10 H
V ADDY V AGNDY V ADDU V AGNDU V ADDV V AGNDV V ADDC V AGNDC V ADDPA V AGNDPA
V DDQ V SSQ V DD V SS V DDQ V SSQ
TL 431 D1
1
R3 2 62 / 2% R2
3
C 48 C 49 C 50 C 10
100 nF
2 7 12 63
+
C7 1 F
6.8 / C 8 2% + R1 1 F 16 / C 51 2% C 52
100 nF 100 nF
4 9
C 53 C9
YIN UIN VIN CVBS
100 nF 14 100 nF 100 nF 100 nF 100 nF 100 nF 61 3 8 13 62 35 34 33 16
C6 C5 C4 C3
SCL SDA
V DDDTO V SSDTO V DD V SS PBQ0 PBQ1 V REFHY PBQ2 PBQ3 V REFHU PBQ4 PBQ5 V REFHV PBQ6 V REFHC PBQ7 PAQ0 ABACUS PAQ1 SDA 9206 PAQ2 PAQ3 V REFLY PAQ4 PAQ5 V REFLU PAQ6 V REFLV PAQ7 H2I2 V REFLC EXSYN AINY HS CLK1 AINU H1I1 CLK2 AINV BLN SYNC VS RESOUTN ADR0 TEST SCL X2 SDA 48 X1 RESIN
32 23 45 36 50 55 46 49 21 22 44 43 42 41 40 39 38 37 31 30 29 28 27 26 25 24 20 57 54 53 17 52 19 51 18 56 47
+ C 13 10 F
C 14 100 nF
C 15 100 nF
UV0 UV1 UV2 UV3 UV4 UV5 UV6 UV7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
CLK1 H1I1 CLK2 BLN VS RESOUTN
C 2 18 pF C 1 18 pF
UES10472
Q1 24.576 MHz
Figure 20 Application Circuit 3
Semiconductor Group 51 1999-02-10
SDA 9206
5 5.1
Waveforms Timing Diagram Data Input/Output Referenced to the Clock CLK1
t WH
Clock CLK1
t WL V QH t THL t TLH V QL
Output Data
V QH t QH t QD V QL
UET10467
Figure 21 5.2 Timing Diagram Clock Skew CLK2 - CLK1
T
t WH
CLK1
t WL V QH t THL t TLH t WL V QH t THL
T
V QL
t SK
CLK2
t WH
t TLH
V QL
UET10468
Figure 22
Semiconductor Group
52
1999-02-10
SDA 9206
5.3
Programmable Data Output Delay: DAT_OUT: Pins PAQ7...0, PBQ7...0, BLN, HS, H1I1, H2I2 and VS
T CLK1
DAT_OUT
Data valid
Data not valid
Data valid
tQH t QD
UET10469
Figure 23
DATDEL 000 001
tQH; min.
6 ns 10 ns
tQD; max.
25 ns 29 ns
The delay times are valid for a clock rate of the analog PLL of 27 MHz.
Semiconductor Group
53
1999-02-10
SDA 9206
6
Package Outlines
P-MQFP-64-3 (Plastic Metric Quad Flat Package)
0.25 min
2.45 max
0.15 +0.08 -0.02
0.88 0.15
2 +0.1 -0.05
H
0.8 0.3
+0.15
12 0.2 17.2 14
1) M
C A-B D C 64x
0.1
0.2 A-B D 64x 0.2 A-B D H 4x D
A
B
64 1 Index Marking
1)
0.6 x 45
GPM05250
Does not include plastic or metal protrusions of 0.25 max. per side
Figure 24
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information".
SMD = Surface Mounted Device Semiconductor Group 54 Dimensions in mm 1999-02-10
14 1) 17.2
7 max

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